Consortium Course Material


The background of this cutting-edge technology is the race, that between the dramatically increasing market demands of the multifunctional electronic products, and the continuously shrinking space of processors and circuit boards challenging the physical limits of silicon and manufacturing technique. To short the time-to-market and save money, both the chip-makers and chip-purchasers give the way to a revolutionary concept, an SoC solution.


The general meaning of SoC(short for System on Chip) is quite self-explanatory. Only one single chip or chipset embraces and properly integrates various silicon components and functional elements in a large number to meet all the required specifications, especially applied to electronic systems such as mobile telephones, cars, aircraft, televisions, computers, PDAs etc. [11]


We integrated a general-purpose micro-processor, Real-Time Operating System (RTOS), some embedded memories and Digital System Processors (DSP) into one chip. There are also some peripheral blocks, such as AD convertor. [2]

Supporting functions for system configuration are also provided including the relevant interfaces, I/O ports, and other intellectual property components where system level considerations such as power optimization, synchronization, testability, conformance and verification are crucial. [3] All the kinds of functional models and subsystems are connected by the bus.


The benefits of SoC are obviously. From your experience you will find the size of each chip is significantly reduced into a thinner board with a better performance and lower power consumption. All the subsystems interconnecting with each other reduce the chips connection either, which is quite good news for system total cost.

Compared to SoC, IC design is different. The connection delay between different chips on a PCB and the unsatisfied reliability of PCB restrict the system performance. Especially when multimedia, network and mobilization become the main trend in the microelectronics production, much more complicated system and much larger scale chip result in the VLSI(Very Large Scale Integration). Traditional IC design can not be competent any longer where wire was used to connect the logical gate. [4]

When it comes to SoC, it stands on the system level rather than functional circuits, incorporating process mechanism, module algorism, imbedded software, chip architecture and even component design. The main conception of it determined SoC design must follow a Top-to-Down design method. Many researches show that under the same manufacturing condition, SoC can be more competent than IC design to fulfill high level requirements.

There are three essential aspects Of SoC technology:

  1. Mixing hardware and software co-design
  2. Based on IP technology
  3. Glue logic techniques between IP modules

The SoC design typically includes: [5]

  • General-purpose programmable processor (ARM)
  • Special-purpose processor (DSP processor, TI C5x)
  • On-chip memory
  • HW accelerating function units (MPEG, JPEG, Baseband Transceiver, Encryption Engine, etc.)
  • Peripheral interfaces (GPIO and AMS blocks)
  • Embedded software

Therefore, SoC design is more flexible and giving more freedom to designers. The degrees of freedom stem from the process element types and characteristics, their allocation, the mapping of functional elements to the process elements, their interconnection with busses and their scheduling. [6]What is more, it has nothing to do with the PCB basic design, which greatly improves electromagnetic compatibility.


System design as a process starts with clarifying user's purpose and no timing or implementation details is given. That is the Specification model which only captures the algorisms behavior.

Architecture model is the first timed model taking computing time into account. In this stage, function behaviors are mapped to processing elements.

Communication model allows the user to select busses and protocols. The Specification Model can be mapped to physical busses and protocols.

Implementation model: synthesis as the last step. As a result of the hardware synthesis, a cycle accurate of each hardware processing element is created. Now, all of the functions described previously are mapped to hardware and all hardware is defined down to the RTL level.

The whole design ends with delivering to users ideal products with all the expected functions and a reasonable price. [6]


The design freedom of SoC leads ultimately to highly specialized chips and cost efficient production. However the newly gained freedom in design places a burden on the SoC designer. [6]

Not only the applications defined strict requirements, the environment posed other requirements like cut down the cost, lower the power consumption and so on.


The problems can be broken into the following three aspects:

  1. the interconnection delay is more and more important than the gate delay. In the deep sub-micron world, the system load from routing wire on the board has become a major factor of timing delay and differences. On-chip
  2. interconnection wire has not only the delay, but also power dissipation.
  3. the feature size is so small that the chip defect is inevitable. When the feature size is smaller than 65 nm, the static power will exceed 50%of the total power. [8] We should use autonomous reconfiguration technique to defect tolerance, failure tolerance and error tolerance to avoid the error in design.
  4. the leakage current and power dissipation become very important.


SoC can be a complex electronic system integrated in one chip, making the system scale is growing larger and more powerful, it is mainly benefited from technology updates, such as deep sub-micron 0.18m, 0.13m, greatly increased the chip performance, enabling higher-speed chips, with an area smaller, to achieve lower power consumption, but also for SoC designs has brought some new difficulties

[11] Course Overview: MSc System-on-Chip, Dr Peter R. Wilson


  1. SOC Consortium Course Material, Prof. An-Yeu (Andy) Wu, 2008/9/24
  2. Ethernet Controller SoC Design and Its Low-Power DFT Considerations, ZHENG Zhaoxia,ZOU Xuecheng, YU Guoyi]Joury of natral scinces, 2008 Vol 13, No.1 ,075-080
  3. Leaflet_SoC, YOGITECH SPA 2005
  4. Journal of Hubei Water Resources Technology College, Vo 1.2, No.1, Mar. 2006
  5. Surviving the SoC revolution - A Guide to Platform-based Design, Henry Chang et al, Kluwer Academic Publishers, 1999
  6. System-On Chip Modeling and Design, Pramod Chandraiah, Hans Gunar Schirner, Nirupama Srinivas and Rainer Doemer, CECS Technical Report 04-17, June 21, 2004
  7. A. Gerstlauer, R. Doemer, J. Peng, D. Gajski: "System Design: A Practical Guide with SpecC", Kluwer Academic Publishers, Boston, June 2001. ISBN 0-7923-7387-1
  8. Evolution of MPP SoC architecture Techniques , SHEN XuBang Sci China Ser F-Inf Sci|Jun.2008|vol.51|no.6|756-764

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