Gated ring oscillator mainly
Gated ring oscillator mainly
Abstract
This report presents a design of gated ring oscillator mainly using inverters and D_flipflops. Beginning with a brief introduction, the intrinsicstructure of CMOS is demonstrated implying that the natural delay from CMOS gates is desirable in an oscillator. A gated ring oscillator circuit is created and estimated in LTSpice. Then statistical analysis is made withcurve fitting in Matlab. To meet the specification, inverters and D_flipflops are supposed to be placed in a certain pattern which generates the required frequency.To find the most suitable pattern, a compromise must be made based on the consideration of power consumption and precision of frequency.
I. INTRODUCTION
typical CMOS embracing a pair of PMOS and NMOS can be considered as a simple inverter. The digital behavior logic is:
N Channel enhancement mode MOSFET turns on when a positive voltage is applied to its gate as source signal while a P channel MOSFET turns off. Oppositely, P Channel enhancement mode MOSFET turns on when a negative voltage is applied to its gate as source signal while n channel MOSFET turns off.
From Fig.2, a test circuit for CMOS is simulated in LTSpice. Fig.3 is an analog status analysis of NMOS and PMOS. The whole process of coming source changing from 0 to 1 can be divided into 4 different stages.
In zone 1, Vin bellows the threshold voltage Vtn and NMOS is cutoff while PMOS is working linearly. When Vin accents across the threshold in zone 2, NMOS gets into saturation. Once Vin reaches VDD/2, all PMOS and NMOS come into saturation immediately, then NMOS starts to work in linear condition in zone 3. Finally, PMOS is cut off when Vout falls below the threshold voltage Vtp in zone4.
Compared to BIJ, inverters in terms of CMOS have obvious advantages. Firstly, the input impedance is much higher than BJT circuit which means the standard source load is minimized then circuit will have less load effect. Besides, the gate current is so close to zero on which base the input impedance can be regard as finite. What is more, the threshold voltage is nearly 50%VDD that make the CMOS immune to input signal vibration and large noise margin. However, CMOS is not perfect since delay is inevitable. The drawback of CMOS is circuit board dimension increase dramatically, more and more CMOS components are implanted into them. The interconnection delay accent significantly which degraded the performance and power dissipation. But the imperfection of CMOS is a useful resource for some special applications. Especially in oscillator cases, the looped inverters just take advantage of this kind of delay.If several inverters are strung up like Fig.4, there may be two different situations. One is the number of inverters is odd, and it's a regenerative chain as Fig.5; another situation is the number is even, where it's nonregenerative as Fig.6.
A ring oscillator consists of N inverter stages in a circular chain, where N is odd (Normally at least 5 inverters are used). Due to the odd number of inverters in the chain, there is no stable DC point and oscillates exist in the circuit. The period of the oscillation is determined by the propagation delay tp of each inverter stage and the number of stages N, then T=2*tp*N.
This equation is only valid for 2Ntp>>tf+tr. If this condition is not met, the circuit might not oscillate—one wave of signals propagating through the ring will overlap with a successor and eventually dampen the oscillation.
Delay can be defined as Fig.7.Tf is the falling time of output from 90% to 10%. TR is the rising time of output from 10% to 90%. Tphl is estimated from the 50% VDD during the rising edge of input to 50% VDD during the following edge of output. Tplh is estimated from the 50% VDD during the falling edge of input to 50% VDD during the rising edge of output.
In this experiment, all the inverters are provided identical and specified.
II. METHODS
There are several ways to vary frequency at the output, among which include varying the number of stage N in the inverter chain, or replacing one or more inverters with other gates, such as nand or nor, etc. In order to know the accurate effect of different ways affect the frequency, we compared a group of numbers from different circuits.
1) Inverters
More inverters in a loop mean longer total delay. The statistic result of delay change with the number of NOT gates. But according to the observation and analysis in this experiment, add 2n inverters in the loop does not mean add 2n*td in the total delay. As in Fig.8, the average delay of one inverter is decreased while the number of inverters increases.
2) D_fliplops
Modified D_flipflop with D connected to Q works like T_flipflop. As a frequency division device, it is very useful in time delay as well as phase delay. The delay increases much faster than inverters'. But too many D_flipflops may increase the power consumption as shown in Fig.9. Thereby, an appropriate number of D_flipflop is a compromise of transistor cost and power consumption.
3) Voltage
Voltage is another critical factor to total delay. Fig.10 shows that when voltage supply is too high or too low, slope is much steep indicating that in that period delay is vulnerable to voltage vibration. Actually, when voltage is below 0.7V, this circuit does not work at all; when voltage reaches 8V, circuit fails again. In between, from 3V to 7V delay is generally when voltage reaches 8V, circuit fails again. In between, from 3V to 7V delay is generally stable and the lower the better because lower voltage means lower power consumption. In this experiment, we choose a fixed VDD 3.3V.
In order to get more precise frequency from the ring oscillator, some measures are taken to adjust frequency slightly. One is add capacitance as shown in Fig.12. But capacitance is a kind of passive devices which are very expensive in terms of silicon size and extra specialist layers. Another way is add gates such as NOT gate, NOR gate and so on. In this way, more gates may occupy more chip area and the cost of gates is considerable. What is more, more gates result in more power consumption. However, if additional gates can significantly modify the frequency, it is worth under the high demand of precision. Fig.11 is a statistic comparison between different gates in different position in the Fig.12 circuit. Obviously, add more inverter can change delay very much, and NAND can modify delay much less. Therefore, you can choose different devices in different conditions.
III. DESIGN AND SIMULATION
According to the discussion above, in order to design a 64.38MHz gated ring oscillator, some important parameters should be estimated. It is known that T=2*tp*N.
In this equation, tp is the average propagation delay of inverters, N is the number of inverters and M is the number of D_filpflops. To start with, we measured a circuit with 5stage ring oscillator and one D_filpflop show in Fig.13, the frequency of the output is 699.52MHz, which is much bigger than what we want. However by using the equation and the influence factors discussed above, we can make a tentative plan to reduce the frequency.
As a view of inconvenience in simulator, RC delay models are used to estimate delay:
C is the total capacitance on output node. R is the effective resistance and tpd = RC.
When it comes to power consumption consideration, power dissipates from three ways.
1) The junction leakage currents are caused by thermally generated carriers.
Pstatic = Ileakage*VDD
Their value increases exponentially with increasing junction temperature. As we discussed before, it is the almost zero power consumption in steadystate mode of CMOS.[7]
2) Dynamic power is much larger than static power. Since, Energy/transition = C L * V dd2.[inverter2]
Then, Power = Energy/transition * f
= CL * V dd2 * f.
So, we need to reduce CL , Vdd, and f to reduce power.
3) Power consumed via direct path currents, or in other words, short circuit path between power rails during switching.
Using triangles and VDD >> VT, the power dissipation of the following stage for one transition (either rising or falling edge) is approximated by
Pdp=(VDD*Ipeak*tr/2+VDD*Ipeak*tf/2)*f
=(tr+tf)/2*VDD*Ipeak*f
Td=(tr+tf).
Zero rise/fall times is not a realistic assumption. Ipeak depends on both VGs and VDs. Therefore it is both input waveform and load dependent. Directpath power is typically only about 20% of the dynamic power.
Now, the total power is
Psum=Pdynamic+Pstatic+Pdp=CL*VDD^2*f+VDD*Ipe
ak*(tr+tf)/2*f+VDD*Ipeak
Pdp is the energy consumed by the gate per switching event.
There are several ways to reduce power consumption. From the equation we can easily find that reduce voltage can significantly decrease the power. Besides, reduce switching activity leads to less current pulse occur. What is more, physical capacitance is the smaller the better. Using a lot of negative components such as capacitance should be avoided.
After calculation and a number of experiments, three circuits which have similar performance are listed below.
1) Here comes our first approach, a circuit with 7stage ring oscillator and 4 D_filpflops is shown in Fig15, and Fig16 shows the transient analysis waveform of output. It can be measured that the period T=1.56056e008s (f=64.08MHz), which is very close to our target. Apart from the accuracy of frequency, power dissipation is also an important part what we should take into consideration. Fig.17 show the current flowing in the voltage source.
ELEC6021 RESERCH METHOD  OSCILLATOR DESIGN REPORT
Zheng Cenying, Xie Wei (SoC, Southampton University) Nov. 2009
ELEC6021 RESERCH METHOD  OSCILLATOR DESIGN REPORT
Zheng Cenying, Xie Wei (SoC, Southampton University) Nov. 2009
ELEC6021 RESERCH METHOD  OSCILLATOR DESIGN REPORT
Zheng Cenying, Xie Wei (SoC, Southampton University) Nov. 2009
ELEC6021 RESERCH METHOD  OSCILLATOR DESIGN REPORT
Zheng Cenying, Xie Wei (SoC, Southampton University) Nov. 2009
2) Another way to decrease the frequency is adding extra gates between stages. Add different gates can change the period in varying degrees. The circuit based on this theory is shown in Fig.18, and the period T=1.56842e008s (f=63.76MHz). Fig.19 shows the waveform.
ELEC6021 RESERCH METHOD  OSCILLATOR DESIGN REPORT
Zheng Cenying, Xie Wei (SoC, Southampton University) Nov. 2009
ELEC6021 RESERCH METHOD  OSCILLATOR DESIGN REPORT
Zheng Cenying, Xie Wei (SoC, Southampton University) Nov. 2009
ELEC6021 RESERCH METHOD  OSCILLATOR DESIGN REPORT
Zheng Cenying, Xie Wei (SoC, Southampton University) Nov. 2009
ELEC6021 RESERCH METHOD  OSCILLATOR DESIGN REPORT
Zheng Cenying, Xie Wei (SoC, Southampton University) Nov. 2009
3) The third method is to replace inverters in the ring with other gates which has longer propagation delay. It is not only can reduce the number of inverters, but also cut down the number of D_filpflops. The decrease of components directly leads to the reduction of power dissipation. Fig.21 shows such a circuit with the output period T=1.55361e008s (f=64.37MHz). Fig.22 is its transient analysis waveform.
ELEC6021 RESERCH METHOD  OSCILLATOR DESIGN REPORT
Zheng Cenying, Xie Wei (SoC, Southampton University) Nov. 2009
ELEC6021 RESERCH METHOD  OSCILLATOR DESIGN REPORT
Zheng Cenying, Xie Wei (SoC, Southampton University) Nov. 2009
ELEC6021 RESERCH METHOD  OSCILLATOR DESIGN REPORT
Zheng Cenying, Xie Wei (SoC, Southampton University) Nov. 2009
ELEC6021 RESERCH METHOD  OSCILLATOR DESIGN REPORT
Zheng Cenying, Xie Wei (SoC, Southampton University) Nov. 2009
Fig.22 Waveform V(vout) in circuit 3
To sum up,
ELEC6021 RESERCH METHOD  OSCILLATOR DESIGN REPORT
Zheng Cenying, Xie Wei (SoC, Southampton University) Nov. 2009
Circuit1 
Circuit2 
Circuit3 

Output frequency 
64.08 MHz 
63.76 MHz 
64.37 Mz 

Number Of devices 
D_fliplops 
4 
4 
3 
inverters 
6 
4 
2 

Nands 
1 
1 
3 

Add Gates 
0 
2 
0 

Current flow in source 
upperlimit 
0.7mA 
0.8mA 
0.6mA 
lowerlimit 
4.5mA 
4.5mA 
1.8mA 
Table1 Comparison between 3circuits
By comparison (shown in Table1), the third circuit is going to be our first choice. It not only provides a more accurate frequency, but has the least power dissipation as well.
IV. APPLICATION
FullCustom Ring oscillator can be used in many applications, such as onchip clock distribution schemes, clock recovery circuits, sensor sensing the frequency of oscillator varies with the parameter as well as DLL in FPGAs.
V. CONCLUTION
In this paper, we started from the introduction of CMOS imperfection to its usage as ring oscillator. Then by discussing the influence factors of the output frequency of ring oscillator, three practicable circuits are presented after many experiments using LTSpice. Comparing the frequency accuracy and power dissipation, the circuits with 3 D_filplop and 5stage ring oscillator, in which 3 of the stages are NAND gates, is the best one we provide to generate a 64.38MHz signal. Indeed, there are ways to improve the circuit to a more accurate frequency and less dissipative power. For example, by arranging and assembling different gates in different position of the circuit. Some more influence factors should be taken into consideration and a lot more experiments are needed in our future study.