Market growth in semiconductor technology

INTRODUCTION

The market growth in semiconductor technology continuous unabated high performance transistor technology in various applications. The trend direction is to down scaling the diameters of the integrated circuits (IC) components and also increase in demand for computational power in various applications. Transistor scaling is depends speed versus power. Transistor speed depends on the drive current. The power consumption depends on the transistor leakage current. According to the International Technology Roadmap for Semiconductors (ITRS) [] for the high performance applications like microprocessors the electrical gate oxide thickness (EOT) needed by 2007 should be less than 1 nm and the gate leakage current should be less than the 103 A/cm2 at 100oC. For lower power application like cell phones the major factor is power consumption and the leakage current is less than 1.5x10-2 at 100oC by the year 2006 with the EOT = 1.6 nm. These requirements cannot be meat by the SiO2 gate dielectrics because of leakage current, direct tunneling, boron penetration and polysilicon depletion. These problems are explained in detail in the following chapters and also due to the thickness of the dielectrics. The gate dielectrics with higher permittivity may solve these problems by providing low leakage current with the equivalent EOT [].

This leads to the search for high-k dielectric materials which satisfy the properties and manufacturing limitations. [,]. Metal gate electrodes are necessary to eliminate gate depletion problems they are connected with polysilicon gate. In addition to the gate depletion polysilicon gates also suffer from Fermi level pinning on high-k dielectrics []. This issue leads to investigation on metallic gate electrodes on high-k dielectrics. Metal electrodes like Ru, TaN, TaSixNy eliminate the Fermi level pinning problem, But creates positive charge in the dielectric. The focus of this work is to report that metal gates can substantially enhance the positive charge formation and explore the source of enhancement []. And also focus onhow the TaN gate effects the positive charge formation in HfO2/SiO2 stacks under positive gate bias stresses and in the negative gate bias stress.

Boron penetration:

The CMOS devices are scaled below <100 they are several mechanical stress problem still remains and several method have been proposed to overcome.

Channel Doping:

To adjust the MOSFET threshold voltage Vth to the required circuit design, the channel doping is required. The doping is carried out by ion implantation, a thin dummy oxide film thermally grown on the subtract to prevent the surface form contamination as shown in the figure 1.

This dummy oxide film is removed prior to the gate oxidation. Figure 2. Shows the typical CMOS structure with channel doping. In this case N+ polysilicon gate electrodes are used for Both n and p-MOSFETs and this type of CMOS is called single-gate CMOS. The role of channel doping is to enhance or raise the threshold voltage of n-MOSFETs. It is describe to keep the concentration of p tub lower in order to reduce the junction capacitance of source and drain. Thus, channel MOSFETs flows in a deeper path, as shown in the fig this is called shot channel effect, the shot-channel effect is explained in the later section. Thus, heavy doping of the deeper region is effective in suppressing the shot-channel effect. This doping is called deep ion implantation.

Gate Insulator:

For the purpose of high performance transistor, it is important to reduce junction capacitance. In order to realize lower junction capacitance, a diffused channel structure is proposed as shown in the figure3. Because the channel layer exists only around the gate leakage, the junction capacitance of source and drain is reduced significantly.

The gate dielectric determines several important properties and thus uniformity in this thickness, low defect density of the film, low fixed charge and interface state density at the dielectric and silicon interface, small roughness at the interface, high reliability if time-dependent dielectric breakdown and hot carrier induced degradation, and high resistivity to boron penetration are required. Due to the continuous downscaling of MOSFET the thickness of the gate dielectric have been thinner. In general the gate oxide thickness is 7 to 8nmn for 0.4m gate length MOSFETs and 5 to 6nm for 0.25m gate length MOSFETs.

Gate Electrode:

In LSI fabrication processes polysilicon is widely used as a gate electrode because of its resistance to high temperature. The resistance of the gate electrode gives RC delay time significantly. To reduce the resistance silicides of refractory materials have been put on the polysilicon electrode. Polycide, this technique has the advantage of preserving electric and physical properties at the interface between polysilicon and the gate oxide, and the gate electrode sheet resistance is reduced significantly.

Ion implantation is used for the doping of polysilicon gate. In the case of heavy doping dopant penetration from boron-doped polysilicon to the Si substract channel region through the gate oxide occurs in the high-temperature LSI fabrication process, as show in figure 4. When the doping of impurity in the polysilicon is not sufficient, results in decrease of the drive capabilities of the transistor and there is a trade of between the boron penetration and the gate electrode depletion.

The gate electrode depletion which is described in the following section. The boron penetration and polysilicon depletion problems can be reduced by introducing oxynitride as a gate dielectric material. The oxynitride gate dielectric is formed by the annealing process in NH3,NO after silicon oxidation or by direct oxynitridation of silicon in NO or N2O ambient.

By introducing oxynitride gate dielectric the device show better quality and reliability.

Silicon oxidenitride(SiON):

Silicon oxynitride or nitride/oxide stack structures were studied to replace SiO2 as the alternative gate dielectric material. Since silicon nitride (Si3N4) has a higher dielectric constant (k~7) than SiO2, a thicker film can be used for low gate leakage current, reduced boron diffusion, and better reliability.28-30 In addition, proper incorporation of nitrogen (~0.1%) near the Si channel interface may also improve device performance.31 However, too much nitrogen near the Si channel will degrade the performance of the MOSFETs with low carrier mobility and drive current. 32 Actually, silicon oxynitride has been used as a gate dielectric in most advanced high performance technologies. A 1.2 nm thick thin layer with a reasonable leakage current density may be used for the 70 nm node high performance technology. But with the further scaling of the gate oxide thickness to less than 1.0 nm, silicon oxynitride will lose its advantages due to high gate leakage current, high interface state density, and channel carrier mobility degradation.33 In summary, silicon nitride and oxynitride can only provide a near term solution for the CMOS transistor.

Poly-Si Depletion Effects

The depletion problem in the poly-Si gate

To understand the poly-Si gate depletion problem, the difference bias modes of a p+-doped poly-Si gate/ dielectric/n-type Si substrate under three different bias voltages are introduced:

  1. The accumulation mode, VG> VFB where VG = gate voltage, VFB= flatband voltage.
  2. The depletion mode, Where VFB (VT)
  3. Inversion mode, VG

Accumulation mode:

The accumulation mode occurs when the positive voltage is applied in the gate. The positive charge on the gate attracts electrons (Majority carriers in n-type Si substrate) form the substrate to the oxide-semiconductor interface. This results in a higher concentration of electrons near the interface than that in the bulk for the n-type Si substrate.

Depletion mode:

The depletion mode occurs when a negative voltage is applied on the stack. The negative charge on the gate pushes the electrons away for the dielectric/Si substrate. Therefore the n-type semiconductor is depleted of majority carriers at the interface and a positive charge, due to the ionized donor ions, is left in the space charge region. The voltage separation the accumulation and depletion regime is referred to as the VFB flatband voltage.

Inversion mode:

The inversion mode occurs when a negative voltage beyond the threshold voltage is applied on the gate stack under consideration. In inversion, there exists a positively charged inversion layer at the oxide-semiconductor interface in addition to the depletion-layer. This inversion layer is due to minority carriers, which are attracted to the interface by the negative gate voltage.

The ply-Si gate depletion problems always occur when a MOS capacitor is biased into depletion or inversion. Let us consider a PMOS capacitor which has P+ -doped poly-Si gate and an n-doped silicon substrate.

Figure show energy-band diagram that depict the two situations of a PMOS capacitor (without depletion and under depletion). (+ means heavily doped, doping concentration= 1019/cm3).

a) Energy- band diagram of a PMOS capacitor biased to inversion without the depletion in the poly gate.

b) Energy-band diagram of a PMOS capacitor biased to inversion showing the poly-Si depletion region that is formed.

For P+-doped poly-Si gates, a negative bias applied between the gate and substrate causes either depletion or inversion in the silicon substrate. The charge induced in the silicon substrate by this positive. An equivalent negative charge must exist in the gate. For the poly-Si gate, acceptor ions in the P+-doped poly-Si constitute this negative charge, and it causes a depletion region of some finite thickness to be formed in the gate. This depletion region in the gate is the basis of poly-Si depletion. ?p in figure b represent the voltage caused by this depletion. This voltage drop and the depletion layer cause a depletion capacitance.

The effect of this depletion on the total capacitance of an ideal MOS stack is described next. First, we consider an ideal MOS capacitor.

The capacitance, C of an ideal MOS capacitor is give as

C =ke0 = k sio2e0

Where, k is the gate oxide dielectric constant, e0 the permittivity of vacuum.

A capacitor area tox gate oxide physical thickness.

By assuming the same capacitance is achieved using SiO2 as the dielectric, the equivalent oxide thickness given by = tox

Which means a thicker gate dielectric of high permittivity can hold the same gate capacitance as a thinner SiO2 dielectric. The near- term gate dielectric solution in the semiconductor industry has been on years of research and a thorough understanding of their materials characteristics.

Figure3 shows the reader a schematic overview of the total capacitance in the gate stack. The gate dielectric insulates the gate electrode-gate form the Si substrate. Gate electrodes in modern CMOS technology are composed of polycrystalline Si (poly-si) which can be highly doped (e.g by ion implantation) and subsequently annealed in order to substantially increase conductivity through dopant activation (by driving dopants into electrically active substitution site).

a) schematic of Cpoly-dep, cOX and Cinv

b) equivalent circuit diagram of the poly-si depletion capacitance in series with the gate-oxide capacitance.

c) Ideal and not ideal C-V curves.

In this gate stack, the total capacitance is calculated by the formula:

Where,

C: the total capacitance of this gate stack

Cpoly-dep: the capacitance due to the depletion in the gate

Cox: the capacitance of the dielectric

Cinv: the capacitance due to the inversion in the substrate

The depletion capacitance due to the poly-Si depletion is in series with the capacitance of the dielectric. Thus the smaller capacitance of the dielectric is much smaller than the capacitance due to the depletion until the dielectric thickness gats below about 5.0nm.

When the dielectric thickness is < 5.0nm, the capacitance of the dielectric is so large that the Capacitance due to the depletion begins to impact the total capacitance.

The degree of capacitance reduction depends on the poly-Si doping concentration, the higher the doping concentration, the smaller the depletion effect. The doping concentration limits are 1020/cm3 for n-type poly-Si and 1019/cm3 for p-type poly-Si due to solubility for dopant atoms in silicon.

The poly-Si depletion problem will become worse as the dielectric thickness continues to decrease.

High Direct Tunneling Current

High gate tunneling current is the first concern to use the SiO2 gate dielectric in the sub-100 nm MOSFETs. As the oxide thickness scales down below 1.5 nm, the dominant conduction mechanism for the leakage current will be a quantum mechanic tunnelling mechanism, or direct tunneling. The direct tunneling gate-to-channel leakage current for SiO2 increases exponentially as the thickness of the SiO2 gate oxide decreases as shown in Figure 5.12 For a 1.5 nm thick SiO2 layer, the leakage current density will reach ~10A/cm2 when the gate voltage is 1V, which will result in excessively high power consumption. According to the specification from the IRTS, the scaling limit of the SiO2 gate oxide in terms of leakage current should be 2.2-2.5 nm for a low operating power application and 1.4-1.6 nm for a high performance application.

It was reported that transistors with 1.3-1.5 nm thick SiO2 gate oxide could still be used for a high performance application but not for a low power application due to their high gate leakage current density (1-10 A/cm2). 13-14 As the SiO2 gate oxide thickness scaled down below 1.0-1.2 nm, no further improvement in transistor drive current could be achieved.

Concern of ultra-thin SiO2 gate oxide Quantum Mechanic Effects Ultra-thin gate oxide may also lead to a quantum mechanical carrier quantization. 37 The decreasing gate oxide thickness and the increasing substrate doping density will cause a higher transverse electric field in the inversion layer. The sharp bending of the energy bands will cause a significant quantization of the carriers normal to the oxide/Si interface. The quantum mechanic effects occur when the carriers are confined in a narrow potential well. The quantum mechanic effects will cause the conduction and valence energy bands to split into sub-bands. The effective Si band gap increases slightly because the lowest sub-band is above the edge of the conduction band, as shown in Fig.6

(a). Due to the formation of the sub-bands, the charge distribution peak is shifted further from the surface than classical theory predicts, as illustrated in Fig.6 (b). 37 Hence, the centroid of induced charge shift into the Si substrate and a depletion region is formed near the oxide /Si interface, which is equivalent to adding a capacitor in series with the gate dielectric layer. About 3-5 EOT increase will be contributed to the quantum mechanic effects of the Si substrate.37

Chapter 2

Alternative Gate Dielectric Materials

As discussed in the previous section, as the channel length of MOSFETs scales down to sub-70 nm feature size, a corresponding SiO2 gate oxide with a thickness less than 1.5 nm will be required. At this thickness, the conventional thermally grown SiO2 gate oxide will approach its physical thickness limit due to three major problems: exponential increase in tunneling leakage current with decreasing film thickness, poor reliability, and undesirable boron diffusion from the poly-Si gate through the oxide. New gate dielectric material with a high dielectric constant (k) to replace the SiO2 will allow the use of a physically thicker gate dielectric layer while maintaining the same control of inversion charge. With a thicker insulating layer, the concern of a high tunneling current through the gate oxide and other reliability issues may be solved efficiently. using a 3.0 nm thick high-k gate dielectric layer may improve the capacitance by 60% and decrease the leakage current density by 2 orders of magnitude.[]

High-k dielectrics materials like BaSrTiO3 and SrTiO3 suffers from very small band gaps but they produce very high gate capacitances. [] and also high-k dielectrics are not suitable for use in MOSFETS because materials with high dielectrics constant can leads to field induced barrier lowering (FIBL) which can degrade the shot channel effect further []. Other high-k materials like Ta2O5 and TiO 2 also have lower barrier heights and also we have to concern that at high temperature there is a large interaction with poly-silicon or metal gate electrodes. [,]

The dielectrics such as Al2O3 CeO2 and Y2O3 do not provide significant advantages over SiO2 or Si3N4 because they are relatively low dielectric constants.[,] A variety of mid-range high-k materials have been reported as positive candidates for MOS gate dielectrics. These include dielectrics such as La2O3,HfO2 and ZrO2, which have all been proven to be thermodynamically stable on silicon. However, as discussed above, these materials are good diffusers of oxygen resulting in the formation of interfacial layers. Up on temperature annealing another group of dielectrics that have been considered as strong potential candidates involve silicates namely HfSixOy, SrTaO6, ZrSiO4 and ZrSixOy.[] These multi-elemental oxide are compatible with silicon substrate and are thus stable on it.

ZrO2 andHfO2 emerged as promising high-k dielectrics for ultra-thin gate dielectric application almost at the same time and it was reported that both films have promising characteristics such as low leakage current, good interface properties (Dit~10 11/eV-cm2 and and excellent reliability properties [,]. However, during the past several years, hafnium based metal oxides and silicates have received significant attention as the most promising candidates for alternative high-k dielectric applications due to high dielectric constant, large barrier offsets, and thermal, chemical stability with polysilicon gates. In addition, an ultra thin HfO2 gate dielectric with an effective oxide thickness of 0.9 nm was obtained. Lee et al. reported that their HfO2 film maintained its high quality after a high temperature boron dopant activation (950C for 30seconds) and also showed very good leakage current behaviour (0.23 mA/cm2 at Vg = 1 V) [,]. Hafnium silicates, with a dielectric constant around 11 are also being pursued as gate dielectric candidates for the 45 nm gate length CMOS technology [].

Even though many research efforts have aggressively studied and solved several issues associated with the high-K dielectric, there are still many challenges for the process and integration of high k dielectrics.

Alternative Gate Electrode:

From several decades polysilicon is used as a gate electrode in MOSFET devices. However, due to the aggressive scaling of CMOS technology the polysilicon gate technology faces many problems when the gate is biased to inversion mode a depletion layer is formed at the gate oxide and polysilicon interface and this depletion region is added to the total oxide thickness which can decrease the gate capacitance and also decrease the device current and transcoductans. If a thinner dielectric is used the depletion layer associated with capacitance at the poli-Si/gate dielectric interface become significant.

Another issue is increase in sheet resistance of the polysilicon gate which reduces the speed of the circuit. the depletion level of polysilicon gate has been increased to reduce the depletion capacitance and sheet resistance but the doping level of polysilicon is limited to 1021 cm-3 which may not possible to recover the capacitance. As the MOS device scaling is continues further, boron penetration in to the gate dielectric also occur with effects the devices threshold voltage. The Fermi level pinning problems also occur when polysilicon gate electrodes are deposited on high K dielectrics. To avoid this problem metal gates are required to replace polysilicon gate electrodes [].

New metal gates have to obey many requirements which include appropriate work functions, good thermal/chemical interface stability with underlying dielectric and high carrier concentration and process compatibility with current and future CMOS. A metal gate should have an appropriate work function for NOMOS or PMOS devices. This implies a work function of NMOS as ~4eV for NMOS devices and ~5eV for PMOS devices. For CMOS processing midgap metal gates and dual metal gates can be used however with a more complex process integration scenario. due to the easy of integration the midgap work function metals are considered, which are not suitable for the bulk CMOS device scaling due to the high threshold voltage which cannot be reduced by lowering the substrate doping which leads to difficult in controlling the shot-channel effects. Due to this reason we required two different gate metals with work function near to the conduction and valence band edges of Si []. And also perform good thermal stability with the dielectric. In addition oxygen diffusivity should be low and other dopents of the metal gate are necessary. and moreover candidates should have high carrier concentration to avoid gate depletion effect.

Research on alternative metal gate electrodes is going on in different metals including elemental, nitrides, silicates, and alloys []. Metal gate electrodes have been successfully incorporated into the CMOS process with high carrier concentration and they is no gate depletion effect. Reports also explain that metal films have above 1022cm-3 [] carrier concentration higher than the poly-Si films.

Candidates with work function near to 4eV for NMOS such as Al, Ta, Mo, Zr, Hf, V and Ti work function near to 5eV for PMOS such as Co, Pd, Ni, Re, Ir, Ru and Pt. There are also several metal oxides such as RuO2, IrO2, ZnO, MoO2, ReO2, In2O3 SnO2, OsO2, and metal nitrides like TiNx, MoNx, WNx, TaNx, TaSixNy. Typically metal oxide work function is higher than the corresponding metal because of the Fermi level change.

From recent reports Fermi level pinning is occurred when the reaction between the poly

Silicon gated and a metal gated electrode with the underlying dielectric. and future the threshold voltage shift in MOSFET devices. Fermi level pinning occurs when states at the interface are charged and causes dipole which drives the band alignment to change so that a zero dipole will exist. This tends to shift the Fermi level towards the charge neutrality level and hence pinning of the Fermi level occurs at the interface. For Hf-based dielectrics, the interfacial Si-Hf bonds are believed to be the main mechanism creating dipoles. This dipole pins the Fermi level just the poly-Si conduction band and thus increases the threshold voltage for both NMOS and PMOS devices [].

Metal alloys

Introduction:

Dual metal electrodes like Ru, Ru-Ta alloy, TaN and TaSiN on low EOT single layer HfO2 and stacked HfO2/SiO2 gate dielectrics will be presented. We know that HfO2, HfO2/SiO2 and SiO2 have a similar work function. In this chapter we are going to discuss the properties of different metal alloys with underlain electrodes.

As we discussed earlier metal gate electrodes are needed to reduce the gate depletion problems which are associated with usual polysilicon gates. And also polysilicon gates also suffer from Fermi level pinning on high-K dielectrics []. This leads to introduction of metallic gate electrodes on high-K dielectrics. For bulk CMOS devices, the work function of metals should be near the conduction and valence band edge of silicon, i.e ~5.2eV for PMOS and 4.1 eV for NMOS devices [].

Different type of metal alloys with their properties are explained in details

For low ETO single layer HfO2 and HfO2/SiO2 gate dielectrics the dual metal electrodes such as Ru, Ru-Ta alloy, TaN and TaSiN were investigated. HfO2 and SiO2 the work function values were similar. All these metals have good electrical properties on SiO2 gate dielectrics. These properties provided the justification of analyzing them on high-k dielectrics.

Ru-Ta Alloys:

Ru has high work function 5.1 eV, very low resistivity 6.7?cm, high melting point 2334oC. Thermal expansion coefficient is 6.4x 10-6oC Its atomic mass and radius is 101.1 and 1.30A. and have hcp strecture with lattice parameter of a= 2.71A c=4.18A it has been extensively studied for DRAM research, forms metallic oxide, it have been well suitable to research in DRAM, it forms metallic oxide, easily etched. It has problems on SiO2/HfO2 at high and low temperatures and also forms toxic RuO4 forms at the oxidation state when Ru is exposed to air/H2O at the room temperature to 200oC, a thin oxide

TaN:

Ta is bcc structured material with atomic radies of 1.45A and mass of 180.9, lattice parameter of 3.30A. and thermal expansion coefficient of 6.3x10-6/oC it has many advantages for metal gates such as high melting point 3017oC,low resistance 6.7?cm,work function 4.2eV and low work function 4.2eV it is easy to etched and easily alloyed however bad contact and high reactive with underling dielectrics. Tantalum nitride appeared to have the correct combination of properties required of a gate electrode of the metal nitrides []. Ta1-xNx with x=0.5 to 0.6 found to have the work function of 4.5-4.6eV on SiO2 about 0.25eV larger than that of Ta. Thermal stability on SiO2 can be improved by nitrogen inclusion from 400- 500oC for pure Ta to above 800oC for TaN films. Ta also reduces the thickness of dielectric and reacted with Si forming TaSi2. Thermal stability also improves by the incorporation of nitrogen on SiO2 from 400-500oC for pure Ta to above 800oC for TaN films.

The nitrogen within the dielectric was propositional to the N2 during the deposition of the gate. During sputtering nitrogen was introduced in to the dielectric tends to diffuse to the SiO2/Si interface causes negative shift in the flatband voltage under rapid thermal anneals. When the oxide layer is less than 35A the Ta1-xNx film can diffused through oxide since the Ta-N bond also be reduced by the Si substrate. However this mechanism cannot be happened when we use lower N content with thicker dielectrics. The drawback of Ta1-xNx films is providing thermal stability near midgap work function which is not appropriate for bulk devices. However these materials are still useful for 1. SOI gate electrodes, 2. Capping layers for CMOS bulk devices. But still investigation is going on high-k dielectrics under Fermi level pinning and thermal stability of TaN gate problems.

TaSixNy:

it has been reported that the TaSixNy metal electrodes are compatible with NMOS devices, provides the right competitive is achieved []. it was found that work function 4.2v~4.4v is provided when TaSixNy films on SiO2 and also compatible with NMOS devices and give good thermal stability up to 1000oC in minimum change of EOT, while demonstrating low leakage current. The stability of TaSixNy gates are improved because of the presences of Si and N in the gate electrode, which improves the diffusion barrier properties and also improves the film micorstrecture at the gate-dielectric interface.

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