Statically routed network on chip



Network on chip is an efficient communication architecture built on chip for system on chip architectures [11]. It allows integrating a large number of processing, computational as well as storage blocks on a single chip [8]. Network on chip architectures has overcome a large number of system on chips disadvantages and are also scalable [9]. In this proposal, we try to define different protocols of a network on chip; with an effort to build it with a special concept of colors. To the best of our knowledge this is an effort to build different protocols of a network on chip which could avoid traffic by describing it with the help of waveforms and necessary figures.


As we know that the number of transistors/chip in any system is to increase beyond a billion, which means that the technology scaling which is been less than 50 nm at the end of this decade [1]. So, we will have to apply some new methods to manage this huge number of transistors on chip, and for the virtue of this System on Chip and Network on Chip are the two main implementation approaches [9]. Presently, we see there are a lot of products, such as cell phones and even portable computers are all implemented on a silicon chip [15]. Due to ever increasing number of transistors [15] they will have a complex design and also long time to market [14]. As traditionally, communication between processing elements was all based on buses [10]. However, for large multiprocessor system on chips, that too with many processing elements it is expected that the bus will become a bottleneck from the point of performance, scalability and also power dissipation; in order to overcome this network on chips have been introduced[1]. We know that the wires can be scaled only to some extent and no attempts can be made in the future to further scale the number of wires [8][9]. This problem is overcome by network on chips where it can be scaled to any limit by just reducing the number of nodes in the network.

Network on chip is a new era of communication within a system [14], where the communication between different cores is undergone not by the help of wires but with a special routing technique. Network on chip provides efficient communication [13] between all the cores in a system on chip [14]. The communication takes place by the help of packets where each one of it, takes a specific route as designed by the programmer. This will make use of three different types of packets in order to make or break a connection between different cores or systems on a system on chip. A new concept of colors is been introduced which will help in less power consumption over traditional wire topology. This is interesting because most of the todays networks on chip designers are struggling for a way to come up with a network which gives better performance with reduced power consumption. The theme to choose this project is to build an efficient network on chip by introducing the concept of colors along with a few protocols which is helpful for the transmission, flow and reception of data packets in the built network and to study the working of it.


Statically routing of packet is a technique where the designer of the network decides the forwarding of packets from one core to several different cores within the network. For the virtue of this, there are three different types of packets made use of:

  1. Route establishment packet.
  2. Data packet.
  3. Route destruction packet.

The concept of using three different types of packets reflects the title statically routed network on chip where the network makes use of static methods for routing of packets in the network. Once the network is built successfully, a route establishment packet is forwarded from the source point i.e the core from which the packet has to be forwarded to the destination point i.e where the packet has to be destined. This type of packet establishes a fixed route for a specific kind of a packet where the concept of color is made use of. The route establishment packet marks the route with a specific color which the data packet makes use to reach the destination core from the specific source point. Once the route is set, corresponding data packets of the same color is forwarded from the source till it meets its destination. The use of color in the packet neglects the fact of repeatedly specifying the source and destination address in the data packet which helps in very less power consumption as well as using fixed route without the occurrence of much traffic. Following figure shows how systems transmit packets in the network on chip in order to attain communication. Different colors are used to indicate different routes that are fixed by sending route establishment packets in order to transmit data packets through the route. Once when there is no need for the communication link and the transmission of data is successful the color route is subsequently destroyed by sending a route destruction packet.


This is a simple node architecture [13] which consists of

  1. 5 bus segments
  2. Control signals Enable Strobe
  3. Buffers

Bus segments are of 16 bits size and the control signals (enable and strobe) are each 1 bit in size. The two buffers in the node are 512 bits each and are accommodated to save data packets during its transmission. The significance of using two buffers is explained in detail at the later stages.

In order to accomplish a network on chip, many of these nodes are connected together using different topologies to build a network. When many of such nodes are connected together and to different cores in a system, communication between them is possible. A packet of several bits of a particular kind (in our case color) travels from its source node through many of such nodes in order to reach its destination node and its corresponding core in a system.

As explained above there are many topologies in a network on chip, few are:

  • Mesh [2]
  • Torus [7][6]
  • Star [4]
  • Octagon [3]
  • SPIN [5]

In all these topologies mesh topology is simplistic in nature and has gained maximum considerations by the designers [1].


Figure shows the network on chip architecture. In fact this is just the replica of a number of nodes which are connected to one another in all the directions to come up to this architecture [13]. The architecture shown below is a simple example of a mesh topology [1] which is of a matrix 4*4 [6]. There can be any number of nodes in the network and also can be connected in any fashion. The nodes in the network are connected simple excluding the control signals so as to retain the simplicity of the network.


In order to attain communication in a network on chip firstly, a packet known as route establishment packet is been transmitted which contains information about the type of color, source and destination address of the packet, directions it needs to follow, as well as the number of nodes it needs to pass through(counter) in order to reach the destination. This type of packet is transmitted to fix a colored route for the forthcoming data packet. And all these information about the source and destination address, type of color, directions as well as counter is been stored in the routing table. Next, a data packet is been transmitted where in it contains no additional information else than the type of color. When a particular type of colored packet is recognized in the network, the routing table provides additional data such as the number of hops through the nodes and respective directions it need to follow in order to reach its destination. The routing table plays an important role by maintaining the information of all the packets in the memory. When all the particular colored data packets are transferred from the respective source to its destination a route destruction packet is transmitted to erase the information about this particular packet in the routing table.


A protocol refers to a set of standard rules that enables systems in a network to connect and transmit data to one another[12]. In other words protocol is a convention or standard that controls or enables the connection, communication and data transfer between computing endpoints [16]. In our project we could include a few protocols necessary to reduce traffic of packets in the network and to obtain efficient communication between different cores.

  1. A packet can enter a buffer if and only if any one of the two buffers in the node is free (empty). If both the buffers are full then the packet will have to wait until the buffer gets empty.
  2. In order to attain packet transfer, one should request for the segment as well as buffer. Only when any one of the buffer in the node is free, the respective node enables the request and a packet is saved in the buffer and a corresponding strobe signal is sent after the reception of it.
  3. Suppose there are two packets from two different nodes waiting to pass through the same node and only one buffer is empty, then the packet which arrives at the respective node first is allowed and the other packet will have to wait until any one of the buffer in the node is free.
  4. In the timing diagram it is assumed that the black packet is forwarded to some other node when green packet arrives and red packet takes the place of black packet.

  5. When 2 buffers in a node are free, and if two different colored packets from two different nodes want to pass through the same node but both in different directions, then the transfer of packet takes place simultaneously.
  6. Consider a condition when any system core on a system on chip say core A is transferring packets to any other system core on the same system on chip say core B with a particular packet color say red; then if in case core B wants to send some packets to core A simultaneously, then, the color of the packet used by core B should be different from that of core A i.e should be any other color than red in this case. Core B will have to establish a separate route to core A or can also use the same route which is used by core A by sending another route establishment packet from core B to core A.
  7. The mechanism of sending a packet from a system core to several different cores simultaneously on a system on chip is not considered i.e the mechanism of copying a particular packet into several different routes at the same time. So, in order to send the packets to different cores, one should complete transmitting its packets to the first core and then turn on the next. For virtue of this the source core has to first establish a route to the first core, transmit the data packets, and soon after the transmission of packets is completed, the route is destroyed. Next the same procedure is followed to transmit packets to the second core. There is a delay organized for the second and the subsequent core till it starts receiving packets.
  8. It is possible that 2 or more system cores on a system on chip transmit a same color packet to different other system cores. This criteria works only when it is considered that the transmitting route of these packets do not cross over each other; Because if the routes match each other then the network may find it difficult to recognize between the packets and it can so happen that the packets reach wrong destination or some time an horrendous network failure in cases.
  9. There can be numerous routes from one system core to several different destination cores. This criteria works only when all the routes have different colors. All these routes can even cross over as many numbers of times as required in a system on chip.


Network on chips are the emerging network solutions for better system on chip designs. Network on chips have tackled many disadvantages of system on chips. Many network on chip techniques have proven to be efficient for communication in many system on chips designs.

For static routing of packets in a network on chip we made use of three types of packets which are known as route establishment packet, data packet and route destruction packet.

We carried out detailed explanations of the three types of packets i.e the route establishment in a network with the help of a route establishment packet where the details of the forth coming data packet such as the source address, destination address, color of the packet, directions and counter are been carried by the route establishment packet and saved in the routing table, and how the data packet makes use of these information by carrying just the color and the necessary data in order to reach the destination. We also discussed how the communication link (route) between two system cores is destroyed after the communication is successful.

We proposed the architecture of a node in the network on chip and also shown how a small node successfully turns up to be the building block of a network on chip. We also discussed about different network on chip topologies. Mesh topology is made use due to its simplicity in architecture and our network on chip architecture is based on the same topology.

Finally, we are successful in proposing different protocols in order to achieve an efficient network on chip with no constraints. Here, it is an effort made to just example the use of the concept of colors in the network on chip, how this technique will be useful in the near future which will help in avoiding huge traffic of packets in an network on chip. Additionally, the use of colors to represent packets can lead to very less power dissipation in network on chips.


[1] An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models

[2] J. Duato, S. Yalamanchili, and L. Ni, Interconnection NetworksAn Engineering Approach, Morgan Kaufmann, 2002.

[3] S. B. Akers and B. Krishnamurthy, A Group-Theoretic Model for Symmetric Interconnection Networks, IEEE Transactions on Computers, vol. C-38, no. 4,pp. 555566, April 1989.

[4] F. Karim, A. Nguyen, and S. Dey, An Interconnect Architecture for Networking Systems on Chip, IEEE Micro, vol. 22, no. 5, pp 3645, September/October 2002.

[5] Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, and C. A. Zeferino, Spin: A calable, Packet Switched, on Chip Micro-Network, In DATE 03 Embedded Software Forum,pages 7073, 2003.

[6] W.J. Dally and C.L. Seitz, The Torus Routing Chip, Technical Report 5208:TR: 86, Computer Science Dept., California Inst. of Technology, pp. 1-19, 1986.

[7] W.J. Dally and B. Towles, Route Packets, Not Wires:On-Chip Interconnection networks Proc. Design Automation Conf. (DAC), pp. 683-689, 2001.

[8] Journal of System Architecture; Volume 50, Issue 2-3, February 2004, Pages 61-63 Special issue on networks on chip

[9] Networks on chips; Technology and Tools; 2006, Pages 355-383

[10]Journal of Systems Architecture, Volume 50, Issues 2-3, February 2004, Pages 105-128 Special issue on networks on chip

[11] Journal of Systems Architecture, Volume 50, Issues 2-3, February 2004, Pages 65-79 Special issue on networks on chip

[12]Computer Communications, Volume 30, Issue 18, 10 December 2007, Pages 3823-3831 Optical Networking: Systems and Protocols

[13] The 2nd IEEE International Symposium on Networks-on-Chip, April 2008.

[14] L. Benini (Ed.), Integration. The VLSI journal, special issue on Network on Chip, volume 38, Issue 1, pages 1-13, 2004.

[15] HDL chip design by Douglas J Smith. Doone publications.

[16] Communication networks; fundamental concepts and key architectures-Alberto Leon and Indira Widjaja, McGraw hill companies,2001.

Please be aware that the free essay that you were just reading was not written by us. This essay, and all of the others available to view on the website, were provided to us by students in exchange for services that we offer. This relationship helps our students to get an even better deal while also contributing to the biggest free essay resource in the UK!